A System-Level Solution to Domino Synthesis with 2 GHz Application

System structure and a 2GHz product application result are described for a domino synthesis capability that covers all aspects of domino design, from estimation to silicon-ready layout, with custom-class optimization. The described optimization flow, abstraction modes, and key cost factors deliver power-optimized, noise-correct domino performance on complex logic. Introduction Domino logic is employed in high performance microprocessors and similar products for logic blocks needing more speed and functionality than are available with standard CMOS circuits. However, expert custom design has been necessary to effectively and safely use domino circuits as a solution to critical, complex logic. Even if not used on a large percentage of the chip, these circuits tend to cost a disproportionate share of effort and risk. A domino synthesis system can contain this cost if it offers a complete solution from estimation and logic definition to silicon-ready design, with speed and power results that are comparable to custom design. The system described here includes all phases of synthesis. Also reported is a silicon-validated result for a complex, critical logic block on a 2 GHz general-purpose microprocessor product that demonstrates custom-class power and delay results. This paper is an overall, systemlevel description of the synthesis flow, from a state-accurate (RTL) logic file to silicon-ready layout. Description of a complete flow has not been given in the literature, although work on several aspects of domino synthesis has been reported [1-4]. In taking a system level view, in contrast to what has been reported, we describe the optimization flow, the full set of sub-modules, and the key factors that summarize the results from one module for use in iteration with another. Additionally, we report on a silicon validation result. Further contrasts to prior reported results are referenced in description of each module. The design and circuit requirements that motivate a system-level synthesis solution are described first. The system-level architecture section describes the interlocking design of the major system CAD blocks and its designerdriven features. The section following outlines the design flows and sub-components of the major system modules. Demonstration results are covered in the final section. Domino Synthesis System Requirements The key design requirement of a synthesis system is to raise the designer level of abstraction in both more rapidly producing a specific logic block and in iterating its design while optimizing the overall chip. The designer deals with logic partitions, optimization factors, and block specifications – rather than meeting noise margin on some specific wire route, for example. Thus, the system must completely model all verification parameters and output tape-out quality design. While the system should produce correct and effective design by default, it also must allow designer intervention at as high a level of abstraction as possible or at as low of a level as needed. Designer skill and knowledge, about the larger application, that is neither in the block spec nor in the optimization criteria, can have important leverage. Additionally, domino synthesis system is allowed no simplification that limits application to complex logic. It’s important to understand this because it impacts every aspect of the synthesis flow. The domino circuit advantage is in implementing complex logic with much less speed degradation than found using standard CMOS gates. Especially with highly scaled technologies, any NAND-NOR logic function that results in >3 series p-devices is not viable in a standard CMOS gate, but this same logic function can have relatively high speed and reasonable drive capability in a domino gate. This is illustrated with Fig. 1 example of a complex domino gate compared to a CMOS gate with the same function. If a logic block does not get leverage from use of complex domino gates, then it probably can be implemented with less power using standard CMOS gates.